Phase Accumulator

Principle of operation

As depicted below, the phase accumulator is clocked by a fixed frequency master clock and with each active clock edge it increments the phase angle by a usually programmable increment f. Since any overflows of this accumulator are ignored, its output values cycle between 0 and 2ρ-1 (with ρ being the width of the phase accumulator). These numbers are interpreted as angles and are therefore (virtually) scaled to a range of 0 ~ 2π.

The master clock has a fixed frequency and therefore the phase increment f determines the frequency of the generated output wave according to the following relation:

fo = fclk * f / 2ρ

It becomes obvious from this equation, that the frequency resolution is determined by the bit size ρ of the phase accumulator. The minimum frequency step is therefore Δf = fclk / 2ρ

Typical accumulator bit sizes are 28 or 32 bits, sometimes even more. For a master clock frequency of 100 MHz, this relates to minimum steps of 373 mHz or 23 mHz respectively. Such a frequency spacing can be considered continuous for most applications. It is much better than the usual spacing of a PLL, which is mostly between 5 and 25 kHz.

The phase accumulator must be able to perform the add operation within one clock cycle. As its result is needed for the next calculation, there is no chance for further optimization by pipelining. The critical path is the carry generation for so many bits. An FPGA architecture should therefore be chosen with an eye on its carry propagation speed for these rather long accumulators.

One could also consider an architecture with multiple accumulators running in parallel, each one of which starts at a unique phase offset and increments by a respective multiple of the phase increment. Their outputs are multiplexed in a suitable way to provide the proper result to the following phase-to-amplitude converter. Each accumulator could then run at a reduced clock speed and implement pipelining as appropriate. While such an architecture might have advantages for extremely long accumulator sizes (e.g. 48 bits), the overhead in terms of logical FPGA gates does not seem to be worthwile for the applications described here. It also seems rather complicated to change the frequency, because each offset would have to be updated with the same clock edge after any frequency change.