Generating a Timing Diagram

DrawTimingDiagram opens two windows, one for the input commands and one to display the timing diagram. Both windows are initially empty. You can type commands in the input window. Try the following sample and click the start button:

$s "clk0"

$t "         lllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhll"

The output window displays the generated timing diagram, which you can select and copy to the clipboard. It can then be pasted to any text editor:

            ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐ 

clk0        │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │ 

         ───┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └─

Commands

Commands start with a $-sign, which is followed by a single character. Commands are followed by a parameter enclosed in quotation marks. The following commands are supported:

Timing ($t)

The timing command is used to specify the timing of a single signal. It draws a timing diagram consisting of three individual lines. Each character in the parameter string defines the signal level of the next time interval. The following signal levels are supported:

l: low

h: high

z: high impedance

x: unknown

X: high or low

r: rising edge

f: falling edge

The lower-case x means an unknown value, which may be high, low or high-impedance. The upper-case X excludes the high-impedance state. Rising and falling edges are actually the same as "lh" and "hl" but they display an up-arrow or down-arrow to mark the edge.

Two formatting commands are additionally supported:

 : insert a space

~: insert a break

Other characters are ignored.

Signal Name ($s)

The signal name command $s sets the name of one or multiple subsequent signals. It must precede the $t command. The defined signal name will be used for any subsequent signal, unless replaced by a new signal name. The signal name is displayed in the middle row of the timing diagram.

Label ($l)

The label command simply displays text as specified by the parameter string. It is a one-to-one copy with the only exception of a circumflex, which will be replaced by a up-arrow (↑).

Here is a more complex example, which illustrates the possibilities:

Input

$s "clk0"

$t "         lllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhl ~ hhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhh"

$l "            |tclk |"

$s "srd"

$t "         xxxxxXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ~ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXxxxxxxxxxxxxxxxxxx"

$l "                  ^ sampled here"

$l "              |---| tsu                                                ~                                          |--| th"

$s "saddr"

$t "         xxxxxXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ~ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXxxxxxxxxxxxxxxxxxx"

$l "                  |-------| > 1 * tclk"

$s "sena"

$t "         lllllllllllllllllhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh ~ hhhhhhhhhhhhhhhhhhhhhhhhhhhlllllllllllllllllllllllllllllllllll"

$l "                              |-----| second rising clk0 edge after sena = 1"

$s "rising_sena (internal)"

$t "         lllllllllllllllllllllllllllrhhhhhllllllllllllllllllllllllllll ~ llllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll"

$l "                                          ^ transfer read register data to serial output buffer"

$s "falling_sena (internal)"

$t "         lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll ~ lllllllllllllllllllllllllllllllllllrhhhhhlllllllllllllllllllll"

$l "                                                                    transfer serial input buffer data to register ^"

$s "clk0"

$t "         lllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhl ~ hhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhhlllhhh"

$l "                                          |-| > 0"

$l "                                                |---------| > 1 * tclk"

$s "sclk"

$t "         lllllllllllllllllllllllllllllllllllhhhhhhhhhhhhhhllllllllllll ~ hhhhhhhhhhhhhhhhhlllllllllllllllllllllllllllllllllllllllllllll"

$s "rising_sclk (internal)"

$t "         lllllllllllllllllllllllllllllllllllllllllllllrhhhhhllllllllll ~ lllllllllllrhhhhhlllllllllllllllllllllllllllllllllllllllllllll"

$l "                                                            ^ shift next bit in/out"

$l "                                                        |tsu| th|"

$s "sdi"

$t "         xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxXXXXXXXXxxxxxx ~ xxxxxxxxxxxxxXXXXXXXXxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"

$s "sdo"

$t "         zzzzzzzzzzzzzzzzzXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXxxXXXXXXXX ~ XXXXXXXXXXXXXXXXXxxXXXXXXXXzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz"

$l ""

$l "Note: tsu and th depend on the device (see simulation). 10 ns (min) should be enough for all."

Output

            ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐ ~ ──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──

clk0        │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │ ~   │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │

         ───┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └ ~   └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘

            |tclk |

              ┌─────────────────────────────────────────────────────── ~ ────────────────────────────────────────────┐

srd      xxxxx┤                                                        ~                                             ├xxxxxxxxxxxxxxxxx

              └─────────────────────────────────────────────────────── ~ ────────────────────────────────────────────┘

                  ↑ sampled here

              |---| tsu                                                ~                                          |--| th

              ┌─────────────────────────────────────────────────────── ~ ────────────────────────────────────────────┐

saddr    xxxxx┤                                                        ~                                             ├xxxxxxxxxxxxxxxxx

              └─────────────────────────────────────────────────────── ~ ────────────────────────────────────────────┘

                  |-------| > 1 * tclk

                          ┌─────────────────────────────────────────── ~ ───────────────────────────┐

sena                      │                                            ~                            │

         ─────────────────┘                                            ~                            └──────────────────────────────────

                              |-----| second rising clk0 edge after sena = 1

                                    ┌─────┐                            ~

rising_sena (internal)              ↑     │                            ~

         ───────────────────────────┘     └─────────────────────────── ~ ──────────────────────────────────────────────────────────────

                                          ↑ transfer read register data to serial output buffer

                                                                       ~                                    ┌─────┐

falling_sena (internal)                                                ~                                    ↑     │

         ───────────────────────────────────────────────────────────── ~ ───────────────────────────────────┘     └────────────────────

                                                                    transfer serial input buffer data to register ↑

            ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐ ~ ──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──

clk0        │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │ ~   │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │  │

         ───┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └ ~   └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘

                                          |-| > 0

                                                |---------| > 1 * tclk

                                            ┌─────────────┐            ~ ─────────────────┐

sclk                                        │             │            ~                  │

         ───────────────────────────────────┘             └─────────── ~                  └────────────────────────────────────────────

                                                      ┌─────┐          ~            ┌─────┐

rising_sclk (internal)                                ↑     │          ~            ↑     │

         ─────────────────────────────────────────────┘     └───────── ~ ───────────┘     └────────────────────────────────────────────

                                                            ↑ shift next bit in/out

                                                        |tsu| th|

                                                        ┌───────┐      ~              ┌───────┐

sdi      xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx┤       ├xxxxx ~ xxxxxxxxxxxxx┤       ├xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

                                                        └───────┘      ~              └───────┘

                          ┌─────────────────────────────────┐ ┌─────── ~ ─────────────────┐ ┌───────┐

sdo      ─────────────────┤                                 ├x┤        ~                  ├x┤       ├──────────────────────────────────

                          └─────────────────────────────────┘ └─────── ~ ─────────────────┘ └───────┘

Note: tsu and th depend on the device (see simulation). 10 ns (min) should be enough for all.

The monospace font, which was used for the previous timing diagrams, is FiraCode, which can be freely downloaded from GitHub.

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